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Fault modeling and design of dynamic logic.

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Call No.	QA76.63 A26 1998
Author	Adams, Robert Dean
Title	Fault modeling and design of dynamic logic.
Date	1998
Abstract	Today''s fastest microprocessors, logic chips, and even memory chips employ dynamic logic as the key part to achieving advanced performance. Dynamic logic only retains the correct data state briefly and is far less robust than previous technologies but is used due to its significant speed advantage. The circuit topology of dynamic logic is quite different from standard static logic and yet to date the same methods are used to test both. The various dynamic logic circuit families are reviewed and a new one, Quad DCVS, is presented. Quad DCVS uses precharge-high and precharge-law inputs and outputs to avoid the race conditions of a dynamic style recently proposed in the literature. Semiconductor chip hardware and simulation results demonstrate functionality for this family. Simulation analysis is performed to determine operating margin allowing better design of dynamic logic in general. The prior art in fault modeling is presented. Hardware and simulation analysis of thousands of faults is employed to choose proper fault models for dynamic logic. Three fault models specifically tailored for dynamic logic are proposed addressing the ability to retain precharge, the shorting of transistors, and the connection of one input to multiple points. Multiple design-for-testability (DFT) circuit techniques are presented to aid in future technology test and provide evaluation methods for otherwise untestable circuit features. A methodology is proposed to test digital semiconductors internally for voltage potential errors thereby identifying faults. This methodology can be done simultaneously across the chip and replaces a quiescent current leakage test technique which is no longer viable.
Description	1 online resource (x, 223 leaves) : illustrations, plans
Format	application/pdf
Advisor	Cooley, Edmond S.
Subject	Logic programming. ; Electronic digital computers -- Circuits -- Testing -- Mathematical models. ; Fault-tolerant computing.
College	Thayer School of Engineering.
Issuing Body	Dartmouth Dissertations are made available through the Dartmouth Digital Library.
Degree	Thesis (Ph.D)--Dartmouth College.
Copyright	In Copyright. This material is protected by copyright and/or related rights. You are free to use this material in any way that is permitted by copyright law that applies to your use. For other uses, you need to obtain permission from the rights-holder(s). http://rightsstatements.org/page/InC/1.0/
DOI	https://doi.org/10.1349/ddlp.2647

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Fault modeling and design of dynamic logic.

Fault modeling and design of dynamic logic.